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Integrated Circuit Systems, Inc.
AV9154A-39
Preliminary Product Preview
Low Cost 16-Pin Frequency Generator
The ICS9154A-39 is a 0.8mm technology low-cost frequency generator designed for general purpose PC and disk drive applications. However, because the ICS9154A-39 uses 0.8mm technology and the latest phase-locked loop architecture, it offers significant performance advantages that enable the device to be used in high performance systems when clock jitter is a key design issue. The ICS9154A-39 guarantees a 45/55 duty cycle over all frequencies. In addition, a worst case jitter of 250ps is achieved. The CPU clock offers the unique feature of smooth, glitchfree transitions from one frequency to the next, making this the ideal device to use whenever slowing the cpu speed. The ICS9154A-39 makes a gradual transition between frequencies.
General Description

Features
All loop filter components internal 5V operation 16-pin 150-mil SOIC Power-down control of CPU clock and Fixed Clock when PD# goes low Output enable control of all output pins
Pin Configuration
Block Diagram
16-Pin SOIC
9154-39 Rev B 09/18/97
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
AV9154A-39
Preliminary Product Preview Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME 8.33 MHz X2 X1 VDD GND 100 MHz 10 MHz AGND OE FS0 NC GND VDD CPUCLK FS1 PD# TYPE OUT OUT IN PWR PWR OUT OUT PWR IN IN PWR PWR OUT IN IN DESCRIPTION 8.33 MHz output clock.* Crystal Out. Crystal In, nominally 10.0 MHz. Digital power (+5V). Digital ground. 100 MHz clock output.* 10 MHz keyboard clock output.* Analog ground. Tristates outputs when low. Frequency select 0 for CPU clock. No connect (Do not connect to this pin.). Digital ground. Digital power (+5V). CPU clock output. Frequency select 1 for CPU clock. Power-down, shuts off internal clocks and forces outputs to low logic level when input pulled logic low.
Note: The following input pins are pulled-up to VDD internal: 9, 10, 15 and 16.
Functionality
FS1 0 0 1 1 FS0 0 1 0 1 CLK(MHz) 40.0 30.0 37.0 25.0
These frequencies assume an input frequency of 10.0 Mhz.
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AV9154A-39
Preliminary Product Preview Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V Operating temperature under bias. . . . . . . . . . . . . . . . 0C to +70C Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 5V
VDD = +5V10%, TA=0C to 70C
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage 1 Output Low Current1 Output High Current1 Supply Current Output Frequency Change over Supply and Temperature1 Input Capacitance1 Load Capacitance1
DC Characteristics SYMBOL TEST CONDITIONS VIL VIH IIL VIN=0V IIH VIN=VDD VOL IOL=10mA VOH IOH=-30mA IOL VOL=0.8 IOH VOH=2.0V IDD Unloaded, 40 MHz With respect to typical FD frequency CI Except X1, X2 CL Pins X1, X2
MIN 2.0 -35 -5 2.4 15
TYP
MAX 0.8
-16.0 0.15 3.7 32 -48 25 0.002 5 0.4
-30 50 0.01 10
UNITS V V A A V V mA mA mA % pF pF
20
Notes: 1. Parameter is guaranteed by design and characterization, not subject to production testing.
3
AV9154A-39
Preliminary Product Preview Electrical Characteristics at 5V
VDD = +5V10%, TA=0C to 70C
PARAMETER Input Clock Rise Time1 Input Clock Fall Time1 Output Rise time1 Rise time Fall time
1 1
Output Fall time
1 1
Duty cycle Duty cycle, reference clocks1 Jitter, one sigma, 32 MHz-100 MHz clocks1 Jitter, one sigma, 16 MHz-30 MHz clocks 1 Jitter, one sigma, clocks below 16 MHz1 Jitter, absolute, 32 MHz-100 MHz clocks1 Jitter, absolute, 16-30 MHz clock1 Jitter, absolute, clocks below 16 MHz1 Input Frequency1 Power-up Time1 Frequency Transition Time1
AC Characteristics SYMBOL TEST CONDITIONS tICr tICf tr 15pF load, 0.8 to 2.0V 15pF load, tr 20% to 80% VDD tf 15pF load, 2.0 to 0.8V 15pF load, tf 80% to 20% VDD dt 15pF load @ 1.4V dt 15pF load @ 1.4V tjls tjls tjls tjab tjab tjab fin tPO tft to 100 MHz from 25.0 to 40.0 MHz
MIN 45 40
TYP 0.8 1.4 0.7 0.8
MAX 20 20 2 3 2 2 55 60
UNITS ns ns ns ns ns ns % % ps ps ps ps ps ns MHz ms ms
80 100 400 -250 -700 -2 10.0 10
120 150 500 250 700 2 20 8
Notes: 1. Parameter is guaranteed by design and characterization, not subject to production testing.
ICS9154A-39
Figure 1: Typical Crystal Circuitry
Note: Crystal load capacitors are internal to the ICS9154A-39 device and no external components are required. 4
AV9154A-39
Preliminary Product Preview
16-Pin SOIC Package
Ordering Information
Example:
AV9154A-39CS16
XXX XXXX-PPP M X#W
Lead Count & Package Width Package Type
S=SOIC Lead Count=1, 2 or 3 digits W=.3 SOIC or .6 DIP; None=Standard Width
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix
ICS, AV=Standard Device; GSP=Genlock Device
5
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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